1. Technical Field of the Invention
The present invention relates generally to the field of power switch monitoring in sub-micronic circuits.
More particularly, the invention relates to a device and method for monitoring at least one power switch in a sub-micronic circuit, the switch being series-mounted with a logic core between a first and a second potential, the connection point between the switch and the logic core being carried to a third potential, and the switch being biased by a biasing potential.
Embodiments show particularly, but not exclusively, an interest in low consumption applications in very large scale integration systems (VLSI) and in particular during the restarting of a central processing circuit also called logic core, a logic core being for example a ring oscillator, and the restarting (or intermediate operating mode) corresponding to the shifting of the logic core, from a first operating state, called sleep mode (inactive mode), to a second operating state, called active mode.
2. Description of Related Art
In sub-micronic technologies, consumed power depends on the dynamic power as well as the static power. This static power must be reduced during the long periods of inactivity of the logic core in order to ensure, for example, a longer service life of supply batteries.
A simple and efficient method for reducing this static power consists in associating one or more power switches to the logic core, as illustrated in FIG. 1, wherein one single power switch has been represented. The logic core LOG_CORE and the power switch INT are series-mounted between a first potential VDD and a second potential GND, the first potential VDD being, for example, a supply equal to 1.2 volts, and the second potential GND being, for example, a ground. The connection point between the Logic core LOG_CORE and the switch INT forms a virtual ground for the Logic core LOG_CORE. The virtual ground is carried to a third potential VGNDV. The switch INT may be an NMOS transistor (n-channel Metal Oxide Semiconductor), the source of which is connected to the second potential GND and the drain of which is connected to the logic core LOG_CORE.
Usually, in this prior art solution, the switch INT is biased on its gate by a constant biasing potential VPLOA, and in sleep mode, the supply of logic core LOG_CORE is cut-off via the power switch INT, inducing a voltage homogenization in the whole logic core LOG_CORE. To exit this sleep mode and enter the active mode, it is necessary to clear the logic core loads beforehand through the power switch.
Through this evacuation of loads, a very high current, which can lead to different problems such as electromigration and a more rapid deterioration of power supply lines, but also generation of rebounds on these power supply lines, can appear. Meanwhile, these different lines are provided for the supply of neighboring circuits and consequently, if rebounds become too large, functionality problems may arise. Thus, it is necessary to limit these rebounds by limiting the discharge currents of logic cores during the shifting from the sleep mode to the active mode.
Further, by considering the fact that the transistor dimensioning was carried out upstream in order to limit, in the second operating mode, the loss in speed to a relatively weak value, when the gate of the power switch is excited by the biasing potential, the power switch should provide a conduction current sufficient for supplying the logic core, while limiting the drain-source voltage to a few millivolts. Thus, the transistors used are very wide and can conduct very large currents if their drain-source voltage becomes high.
As for logic core discharge, it can generate much larger currents than its dynamic consumption since all capacitors must be charged/discharged at the same time, without forgetting the propagation of glitches due to a mispositioning of the internal nodes.
In order to limit the discharge currents, S. Henzler, al., “Sleep Transistor circuits for Fine-Grained Power Switch-off With Short Power-down Times”, IEEE ISSCC, pp. 302-303, February 2005, teaches the dissociation of the gates of the different switches (or only a part) in order to activate them one after the other with a certain delay. This technique makes it possible to limit the charge/discharge currents by modulating the number of transistors used during the reactivation stage. This number should increase with time as the drain-source voltage at the terminals of the switches decreases. Hence, one should dissociate all gates of the switches, thus implying a more complex routing, a surface loss, and a more important overall gate capacity. Moreover, it is more difficult to precisely monitor the activation sequencing of the various switches, especially when there is a technological variation.
There is a need for a device and a method for power switch monitoring allowing to remedy to at least one of the aforementioned limitations.